Output Expander
need help building a circuit?
Hey, for a project i am trying to design a system that can fully control a large number of relays, and that takes 7 inputs and gives a number of outputs which I am to decide. With the use of an i/o expander, the outputs are supposed to be able to be turned on simultaneously according to the system operator.
this system shoulod use decoders and i.o expanders in some way. I am unsure of how many outputs to give the system as well as how to design the system. I have a good knowledge of the material but am still a little confused on what to do.
Any help would be appreciated, thank you.
how many is a large number? a dozen? a hundred? a thousand?
if you have 7 inputs, are these 7 bits of addressing? or 7 total signal lines? (OR, 7 relay-states? types of commands?)
restrictive scenario:
if 7 total lines, we'd need: V+, ground, clock, request {read,write}, some address bits, and at least a data bit. these add up quickly. if the 7 is the total including each of these, then we get 2 address bits and 1 data bit per cycle. would this imply the device is meant to operate on a serial data stream? (which is a little complicated, but usb is 4-pin anyway.. self-clocking, 4-pin, balanced, if i recall correctly).
in the less-restrictive scenario, { V+,ground,clock,request } are seperate from the given 7 inputs.
then you have 7 bits addressing, that could control 127 relays.
i will assume you have to address 2^n relays, where n is in the range [2..7].
if you need more relays than that, then you could have to cascade decoders, and serialize your control of the circuits. this is done by using higher-order bits from the address-bus to select which of m decoders is being addressed, for some value m; OR, by doing this in a sequence of writes to different areas of circuitry. if serialized, you need to recognize start-of-sequence and (self) device-address parts from the serial datastream, and shift each data bit into the instruction register, which can be as long as you like. (8,16,or 32 bits are common for this. but meditate on layout, board space, relay size, and geometry).
how close to simultaneous is good enough? ~1 ms? or do you need shorter?
if you can get away with some fuzz in the time, then different relays would be selected-and-set on different clock ticks, but each "select+set" is atomic. A 16 MHz microcontroller could flip each one in sequence, at most a few microseconds apart. is that good enough? or do you need nanosecond control?
if they must be the same time down to nanosecond, then "select" is made independent from "set", by using a "ready" signal. in this case, your microcontroller writes a coded value to a special enable address, causing all "ready" relays to then set from this signal.
do you need to test and set the state of each relay? i'm assuming yes. then each one is a bit, and you can arrange for them to assert their state on the data bus if addressed.
a common 4-bit address decoder has 24 pins, and selects from among 16 slave circuits. each slave circuit is either: a single relay latch, which needs V+, ground, clock, latch-select, and data signals, or cascades to a daughter decoder.
clock and latch-select signals may be combined if the logic is asynchronous.
negative logic is common in circuits that float high, like TTL. this is good for tristate logic, where all inactive circuits go to high-impedance (which simplifies multiplexing).
since the relays are mechanical, do you want to be able to measure relay settling time and have failure detection? if so, you want to be able to read whether the relay is in the commanded state. so, each commanded state would have to latch, electronically, and this would optionally give an extra bit of state available to output.
i've seen tricks where the request line was absent, and address bit 0 was used for this, instead. in those systems, you always read from even addresses and write to odd addresses, or vice versa.
likewise, the microcontroller's read is on a different cycle from its write. if its command-signals can switch to high-impedance, (tristate-logic devices, usb devices) then address and data bits could overlap? (ie: use the same lines?)
using both of these tricks would get you to 4 address bits, and up to 4 data bits in the restrictive scenario.
hypothetical, useful bits for a relay to assert on its data bus:
bit 0. current state of this relay [0..1];
bit 1. last-commanded state for this relay [0..1] (optional);
bit 2. ready to switch [0..1] (optional);
bit 3. probably unused
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